The invention relates to field effect devices and to silicon gate field effect devices. More particularly, the invention is directed to a process for forming a self-aligned, silicon-gate field effect device having minimum gate overlap capacitance.
A field effect transistor is a three electrode electronic device formed in semiconductor material such as a silicon wafer. The three electrodes are the source, gate and drain. The source and drain are formed in the silicon wafer, which is of predetermined, n or p, conductivity type by doping source and drain regions with impurities of the opposite conductivity type, i.e., p or n.
In the insulated gate field effect transistor (IGFET) technology widely used in the microelectronics industry, an insulating layer of material such as silicon dioxide (or insulating layers such as silicon dioxide and silicon nitride), the "gate insulator", is formed over the channel region between the source and drain, and the gate electrode is formed over the gate insulator. Application of suitable voltages to the gate, drain and source effect and/or control current flow from the source to the drain.
In a depletion mode transistor, a channel of the same polarity as the source and drain exists even without application of a gate voltage, i.e., for a gate voltage of zero. Conduction is normally at a maximum at zero gate voltage and is decreased or turned off by application of a suitable gate voltage. In contrast, enhancement mode transistors are normally off when the gate voltage is zero. When a suitable gate voltage is applied, the channel is inverted to the same conductivity type as the source and drain, thus providing a conduction path between the source and drain such that application of a suitable voltage to the drain causes current to flow from the source to the drain through the channel.
The small size of field effect transistors presents numerous problems, such as imprecise alignment of the gate structure with respect to the source and drain. Imprecise alignment results in excessive overlap of the gate structure relative to the source and drain and in parasitic capacitance. The speed of operation decreases with increases in the total capacitance between the gate and the substrate. Thus, the addition of parasitic capacitance decreases the speed of operation of the insulated gate field effect device. Furthermore, the thrust of the art of large scale integrated circuits is to shrink the sizes of silicon gate FETs in order to increase both the density of the circuits and the speed of operation of the FET devices. As the channel lengths are shortened the parasitic capacitance due to overlap of gate electrode and source and drain regions becomes an increasingly significant factor in the speed of device operation and thus a limiting factor in increasing the speed of device operation.
U.S. Pat. No. 3,475,234 issued Oct. 28, 1969 to Kerwin et al. and U.S. Pat. No. 3,544,399 issued Dec. 1, 1970 to Dill, are directed to self-aligned silicon gate devices which presumably have reduced overlap. In the self-alignment process described in these patents, the gate insulator is first formed over the channel region, then a layer of silicon (typically polycrystalline silicon) is formed over the wafer. Apertures are formed in the silicon-insulator structure and source-and drain-forming impurities are deposited in the substrate through the apertures. The silicon (1) acts as a mask during the deposition step and prevents doping of the channel region during formation of the source and drain and (2) is itself doped, becoming a conductor suitable for use as the gate electrode. Since the silicon gate electrode is in situ during the formation of the source and drain, the source and drain are formed relatively precisely at the edges of the gate structure, at least in comparison to the alignment attainable with typical metal gate processes. This is because metal gates, usually aluminum, present degradation problems at the temperatures required for diffision. Thus, the metal gate cannot be used as a mask during the formation of the source and drain, but must be formed subsequently in the fabrication process, with the concomitant problems of imprecise alignment.
U.S. Pat. No. 3,921,282 issued Nov. 25, 1975 to Cunningham et al. also uses the gate structure to mask the channel region. The Cunningham et al. process differs from those of Kerwin et al. and Dill in that the silicon gate electrode is formed after the source and drain regions and the field oxide are formed. Silicon oxide is formed over layers of oxide and nitride which cover the channel region and is used as the mask during formation of the source and drain. A thick layer of oxide is then formed on the wafer. The nitride is used as an oxidation barrier during this step, to prevent oxidation of the channel region. The result is a channel region well which is surrounded by the thick oxide layer. The nitride is then removed and the gate electrode can then be deposited over the channel-covering oxide with relatively few alignment problems, for the well precisely defines the channel region between the source and drain, while the thick surrounding oxide reduces the effect if the silicon overlaps the source or drain.
The more precise alignments provided by the above silicon gate processes do not eliminate gate overlap capacitance, however. This is because diffusion is an isotropic process and in diffusing the impurities into the substrate to form the source and the drain, the impurities also diffuse laterally and tuck under the gate. The resulting overlap between the source and drain and the gate structure, of course, results in gate overlap capacitance.
As will be appreciated from the above, it is desirable to have a process for forming semiconductor devices which precisely aligns the gate structure with respect to source and drain regions, without overlap.